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地点：圣地亚哥。资格：熟悉ASIC/SOC设计流和方法论熟悉Verilog/System Verilog，Perl，Python。了解逻辑合成和数字设计。计算机体系结构概念的知识。固定点算术概念的知识。具有行业标准EDA工具的经验：综合和/或静态时序分析，LEC，覆盖。能够在具有迅速变化要求的动态环境中成为自我启动者。 Highly motivated, obsession with delivery quality and customer‐oriented Prior internship in ASIC/SoC related work is a plus Education Requirements Required: Bachelor's, Electrical Engineering, Science, or related fields Preferred: Master's, Electrical Engineering Keywords Linting, Spyglass, Verilog, System Verilog, Power Artist, DFT, DFD, Design‐for‐Test, Design‐for‐Debug, MBIST, ATPG，扫描，ATPG工具，RTL，验证，SOC，UVM，ASIC，SOC
数字设计工程师 - 自动驾驶SOC（条目...
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